A Key Features Analysis of the Galileo GT-48360-L-1 Gigabit Ethernet Switch/MAC with Embedded 1T-SRAM

To reveal the design innovations in the Galileo Ethernet Switch/MAC, we offer a Key Features Analysis detailing the embedded memory including: •Memory interface between embedded MoSys memory and the logic •Memory array structure •Memory array peripherals (word line driver, sense amp) •Refresh circuitry, refresh control, cache, address path associated with refresh •Memory interface •Datapath To fast track your understanding of this device, our Design Analysis will include: •A die photograph, showing the physical locations of device circuitry •List of figures with analyzed functional blocks and related transistor level schematic diagrams indicated •Layout photographs for key areas •Functional block and corresponding circuit diagrams presented in a hierarchical format •Device sizes •Signal list, complete with sources and destinations of schematic signal inputs/outputs Optional Analysis You will want to take a close look at this informative report and may choose to take maximum advantage of our optional offerings. These include: •Design files in Cadence® Analog Artist® or ViewDraw™ format •SI Navigator, a PC application that will save time and effort, by guiding you through the Galileo Ethernet Switch/MAC's circuits