Detailed Structural Analysis I with Options of the Matrix Semiconductor 32Mb 3D OTP Memory

This UBM TechInsights Detailed Structural Analysis with Process and Flow Mask, and IC Cost report on the Matrix 3D OTP Memory provides a comprehensive look at the silicon processing steps involved in the construction of the first memory device to exploit the third dimension. Matrix’s designers have placed programmable anti-fuses at metal line interconnections to store zeroes and ones. This technology may well be the vanguard of a new age in digital content storage and distribution since competes with ROM but does not require huge volumes to be cost-effective. Our report is a comprehensive examination of each level of the fabrication process from passivation to wells. Special emphasis is placed on the structure and materials used to create the anti-fuse programmable elements.

Our Comprehensive Structural Analysis includes:

Package and Die Overview
- Front and back package photos, package x-ray
- Die floor plan, die size and thickness
- Major blocks identified

Detailed Process Analysis
- Detailed Scanning Electron Microscopy (SEM) analyses of critical features, including anti-fuses, NMOS, PMOS, vias, contacts, metallization and dielectrics
- Transmission Electron Microscopy (TEM) of anti-fuse structure and associated interconnect levels
- TEM EDS profiles of anti-fuse and metal line layers
- SIMS analysis of passivation and interlevel dielectrics
- Spreading Resistance Profiles (SRP) to determine carrier concentration through N and P wells

Tables of Critical Horizontal and Vertical Dimensions
- Minimum metal and poly widths, pitches and thicknesses
- Minimum via and contact sizes and spacings
- Minimum NMOS and PMOS gate lengths
- Well depths
- Table listing complete materials stack and processes

Optional Analysis Available
- TEM analysis in an alternate direction or location
- Process flow and mask count analysis
- Scanning Capacitance Microscopy for 2D dopant profiles of wells and S/D regions
- DC I-V characteristics of MOS transistors
- DC I-V characteristics of anti-fuse

Included is the IC Cost information for the Matrix 3D OPT Memory.

This report comes with 5 hours of analyst time.