Logic Detailed Structural Analysis of the Xilinx XC5VLX50 Virtex-5 (UMC 65nm Process) FPGA

UBM TechInsights Logic Detailed Structural Analysis report provides a thorough analysis of the silicon processing steps involved in the construction of this innovative IC. Our report is a comprehensive examination of each level of the fabrication process from passivation to wells.

The Detailed Structural Analysis of the Xilinx XC5VLX50 Virtex 5 includes the following information:

Package and Die Overview including:
· Front and back package photo
· Package x-ray
· Die photo with major functional blocks identified
· Die corner photo (power bussing and edge seal)
· Bond pad photo – typical width and pitch

SEM Imaging
· Cross-sections of bond pad, edge seal, and die edge

General Structural Analysis – SEM and TEM Imaging
· Die size, die thickness
· Number of poly/metal layers
· Cross-sections of critical features including NMOS and PMOS transistors, vias, contacts, metallization, and dielectrics
· Cross-sections of the isolation edge structure protected by a poly line
· Materials analysis of silicides and metals by TEM x-ray spectroscopy (TEM/EDS)
· Compositional analysis ofower inter-level dielectrics below metal 2 by TEM x-ray spectroscopy (TEM/EDS)

Gate Stack Analysis of Core Logic Transistor (XTEM - most prevalent on die)
· Polysilicon and silicide structure (poly levels and/or depositions)
· HRTEM of main dielectrics and interfaces
o Gate dielectric
o Gate sidewall buffers
o Sidewall spacers
o Interface between channel and isolation
· Contact structure
· Metal 1 structure
· Metal 2 structure
· EDS analysis of metal and barrier materials
· Isolation edge geometry

Gate Stack Analysis of I/O Transistor (XTEM)
· Polysilicon and silicide structure
· Gate dielectric thickness (HRTEM lattice fringe imaging)

Layout and Design Rule Analysis (PVSEM - topography at poly)
· SRAM
· Standard cell logic

Critical Horizontal Dimensions
Table of Values of:
· Minimum metal line width, space and pitch
· Minimum poly line width and space
· Minimum via and contact sizes
· Minimum contact to gate spacing
· Minimum NMOS and PMOS gate lengths

Critical Vertical Dimensions
· Thickness of layers comprising each metal and poly level by TEM up to metal 2
o Barrier layers, etch stops, poly depositions, silicides
· Isolation, inter-level and passivation total thickness (SEM)
· Total metal level thickness by SEM for M2 and above
· Gate dielectric thickness (HRTEM lattice fringe imaging)

A comparison of device to competing technologies is also given.

This report comes with 5 hours of analyst time.