Memory Detailed Structural Analysis of the Hynix HY5PS12821C 80nm 512Mb DDR2 SDRAM

The Hynix 80nm DRAM process places them second behind Samsung with a bit density of 9.6Mb/mm2. The Hynix HY5PS12821C 512 Mb DDR2 SDRAM has a die size of 7.7 mm by 7.3 mm for a die area of 56mm2. The device is fabricated in a three metal, four poly stacked capacitor DRAM process employing recessed channel array transistors similar to the RCAT developed by Samsung. The half pitch of tungsten bitlines is 80nm. The SDRAM cell size measures 0.222 mm x 0.222 mm = 0.0500 mm2 = 8F2 where F is the minimum feature size of 0.08 mm.

· 8F2 SDRAM cell is 0.050 mm2
· Recessed channel array transistor (RCAT)
· Aluminum oxide/Zirconium oxide capacitor dielectric
· W/TiN metal 1 bit lines with half pitch = 80nm;
· WSix/TiN/poly 1 word lines;
· Contacts to S/D in the array through poly plugs;
· Periphery W plug via aspect ration of ~9:1;
· a-Si/TiN capacitor top electrode;
· TiN capacitor bottom electrode;
Fuses use top capacitor electrode material (a-Si/TiN)

The Memory Detailed Structural Analysis report offers a device summary table and a variety of images. The highlights are on the analysis of the major process findings including identification and discussion of unique device features and innovations, analysis of reliability and quality of process, identification of process artifacts and commentary on process sequence.

Package and Die Overview including:
· Front and back package photo
· Package x-ray· die photo
· Die floor plan with major blocks identified
· Die corner photo (power bussing and edge seal)
· Bond pad photo

General Process Analysis (SEM)
· Die size, die thickness
· Number of poly/metal layers
· Cross-sections of critical features including die edge, edge seal, NMOS and PMOS transistors, vias, contacts, metallization, and dielectrics
· Cross-sections of the isolation edge structure protected by a poly line· Delineation of source / drain junctions by silicon etch stain
· Cross-sections of flash cell parallel to bitline and wordline
· Cross-sections of bond pad, edge seal,
· Materials analysis of silicides and metals by EDSTEM Analysis of Memory Cell
· Cross-section parallel to wordline
· Polysilicon structure (poly levels and/or depositions)
· HRTEM of main dielectrics and interfaces
· Contact structure
· Metal 1 structure
· Isolation edge geometry

Critical Horizontal Dimensions
- Table of Values with SEM documentation of:
· Minimum metal line width, space and pitch in array
· Minimum poly line widths, space in array
· Minimum via and contact sizes and overlap rules
· Minimum contact to gate spacing in array and logic
· Array transistor dimensions· Minimum NMOS and PMOS logic gate lengths

Critical Vertical Dimensions
· Table of Values with SEM and TEM documentation of:
· Thickness of layers comprising each metal and poly level

· Isolation, interlayer and passivation thickness
· Gate dielectric thickness (HRTEM lattice fringe imaging)
· Main dielectric thicknesses (e.g. HRTEM of interpoly for flash)

Layer by layer topographic views of memory cell at substrate, poly, metal 1 and metal 2

Secondary Ion Mass Spectrometry (SIMS) Analysis of Interlevel Dielectrics
Well and substrate doping profiles by spreading resistance profiling (SRP)

Logic (low voltage) transistor gate dielectric measurement by HRTEM lattice fringe imaging

High voltage N-type (HVNMOS) transistor gate dielectric measurement by HRTEM lattice fringe imaging

Layer by layer topographic views of pitch circuitry at substrate, poly, metal 1 and metal 2.