CircuitVision Analysis on the Memory Array, Voltage Generator, Data Path, Bad Block and Fail Bit Count Control, Power Bussing, and Logic Design Methodology on the Toshiba 56nm 16Gb TC58NVG4D1DTG00 MLC NAND Flash (Engineering Sample)

CircuitVision Analysis on the Memory Array and Page Buffer, Full Voltage Generator System, Full Data Path, Bad Block Control, Fail Bit Count Control, Power Bussing, and Logic Design Methodology on the Toshiba 56nm 16Gb TC58NVG4D1DTG00 MLC NAND Flash provides an extensive circuit analysis on Toshiba's latest single chip 56nm 16Gbit MLC NAND Flash device C58NVG4D1DTG00.

Architectural Overview
The Architectural Overview section contains general information concerning the package and die.
This section includes deliverables such as:
- Package Photographs (Top and Bottom)
- Package X-Ray
- Die Photograph
- Die Map (Physical location of circuit elements)
- Array Information
   o Dimensions
   o Wordline Structure
   o Bitline Structure
   o Spare column
   o Extra block number

Memory Array and Page Buffer
The work will cover circuit extraction, analysis and organization of memory array and page buffer area. It includes deliverables such as:
- Bussing Layout diagram
- Annotated topographical images of page buffers and array peripheral circuitry
- Page Buffers and related circuitry
- Row Decoders and related circuitry
- WL Switches and related circuitry
- Memory Arrays

Voltage Generators System
The work will cover circuit extraction, analysis and organization of entire high voltage generation system. It includes deliverables such as:
- PGM Pump
- VDC
- Reference generator
- PASS Pump
- Temperature compensation circuit
- Oscillator circuit
- POR circuit
- Usage of Internal Vcc in logic, XDEC, Page Buffer, and Pump circuits

Data Path
The work will cover circuit extraction, analysis and organization of entire data path. It includes deliverables such as:
- Bussing Layout diagram
- Hierarchical block diagram of data path
- Data Path Schematics (Complete circuits from DQ pad to memory cell)
   o Page Buffers, Sense Amplifiers and Y Gating (Circuitry immediately adjacent to the memory array)
   o IO Buffers and Latches
   o Data Write Path
   o Data Read Path
   o Data Path Control Circuitry
This Data Path Control Circuitry analysis includes custom digital part or place and routed digital controller part, which is related only to data path, it means I/O scramble, I/O multiplexing and repair circuits.

Bad Block Control, Fail Bit Count Circuitry
The work will cover extraction, analysis and organization of the following circuit blocks in the Toshiba device.
- Bad Block Control Circuit
- Fail Bit Count Circuit

Power Bussing Analysis
The work will cover extraction, analysis and organization of both internal and external power bussing in the Toshiba device. It includes deliverables such as:
- VCC/VSS Bussing Layout diagram
- Internal Power Bussing Layout diagram

Logic Design Methodology Analysis
The work will investigate the design methodology of control logic of the Toshiba device. It includes deliverables such as:
- Use of Place and Route tool or manual layout
- Use of micro controller or finite state machine
- Any use of ROM