Memory Functional Layout of the Spansion 65nm 2Gb MirrorBit ORNAND Flash

The Memory Functional Layout report focuses on key metrics associated with system integration on a chip. The report includes measurements on die size, die thickness and minimum feature size as well as detailed photographs, tables and analysis on die utilization and memory array.

The Memory Functional Layout report includes:

Package and Die Overview
- Device description
- Description of package, x-ray, and die markings

Device Measurements
- Die size, die thickness
- Number of poly / metal layers
- Minimum feature size
- Minimum widths and pitches for all poly/metal levels

Cross-Sections and Images
- High Magnification Die Photo provided as a poster size plot
- Photographs of Package Top, Package Bottom, Package X-Ray, and Die markings
- SEM cross-section illustrating minimum feature size
- SEM topographical image of array storage cell at the poly level.
- SEM images illustrating minimum widths and pitches of each poly/metal level

Functional Overview
- Identification of major functional blocks
- High Level Block Diagram (Developed from publicly available datasheets)
- Textual description of the die structure based on SI experience with similar chips. For example, may include a comparison of the die to a previously analyzed die.
- Annotated die photograph illustrating the location of identified functional blocks
- Physical measurements (length and width) for each identified functional block
- Die area summary with percentage of total area occupied by memory, standard cell, I/O's and any functional areas identified on the die

Memory Details
- Annotated die photograph illustrating the logical size of array and the array sub blocks
- Physical measurements (length and width) for arrays
- Array architecture information, including BL + WL Directions

Techniques Applied:
- Cross-section
- Full chip de-layering up to 6 metal levels
- SEM

The purchase of this report includes 30 minutes of analyst time.