A process comparison of the interconnect Technologies of the latest DRAM and NAND Flash and Logic devices

This report will help semiconductor equipment manufacturers and manufacturing companies answer the following critical question: For future technology nodes, is the industry moving towards a general interconnect-process which can be plugged into various platforms: LOGIC, DRAM, NAND FLASH and emerging memories?”

By comparing various interconnect technologies adopted by the latest 40nm NAND Flash devices and 50nm DRAM devices, UBM TechInsights tries to analyze, compare and provide future insights into this critical technology for achieving performance, reliability, and cost effectiveness of memory and logic products.
List of analyses:
• Basic overview of the devices
• Short summary of active area
• Local interconnects and connection to active area
• Silicides and their usage in local interconnects
• Phosphor doped materials for gettering
• The branching out of metal pitch (compare the ratio of lowest metal level pitch and the last metal pitch)
• Thickness of barrier layers
• Total height of interconnects vs real estate
• Use of low-k
• Transition of last metal level and bond pads.