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CircuitVision Analysis on the DLL and VDDI Voltage Generator found in the Clock Management Tile on the Xilinx XC5VLX50T FPGA Circuit | 2010/07/23
CircuitVision Analysis on SelectIO Buffers of the Xilinx XC5VLX50T Virtex-5 FPGA Circuit | 2010/07/16
CircuitVision Analysis on Select I/O Buffers of the Xilinx XC5VLX50T Virtex-5 (Toshiba 65nm Process) FPGA Circuit | 2009/11/30
Die Level Review of the Xilinx XC3S700A Spartan FPGA Functional Analysis | 2009/04/25
Custom Structural Analysis on the Xilinx XC5VLX85T 65nm CMOS FPGA Structural / Process | 2009/03/31
Custom Structural Analysis including General, Edge Seal and Bond Pad SEM Cross-Sectional Analysis of the Xilinx XC3S700A FPGA (suspected UMC process) Structural / Process | 2008/09/30
Custom Structural Analysis including General, Edge Seal and Bond Pad SEM Cross-Sectional Analysis of the Xilinx XC3S500E FPGA (suspected UMC process) Structural / Process | 2008/09/30
Custom Structural Analysis including General, Edge Seal and Bond Pad SEM Cross-Sectional Analysis of the Xilinx XC3S1400A FPGA (suspected UMC process) Structural / Process | 2008/09/30
A Schematic Report of the I/O Buffer of the of the Xilinx XCV30PQ240AFP FPGA Confidential | 2000/10/30
A Schematic Report of the Block Select RAM of the Xilinx XCV30PQ240AFP FPGA Confidential | 2000/11/30